Pulse width measurements are often an essential requirement in characterizing digital circuits. With the advancements in technology, digital circuits are becoming increasingly faster and such measurements are becoming increasingly challenging. In particular, pulse-width measurements for high-speed digital circuits embedded in integrated circuits are extremely difficult and error-prone as the internal timings are significantly smaller than the signal delays from chip IO pads to external measuring instruments. The IO pads themselves contain buffering circuitry that adds considerable delay and that is incapable of operating at the high speeds of the internal circuitry. If Fmax is the maximum operating frequency of the IO, then only a pulse of width greater than or equal to 1/(2*Fmax.) can be measured by this method.
For this reason, pulse-width measurement circuits need to be integrated with the remaining circuitry of the device.
Existing designs of on-chip and off-chip pulse measurement circuitry utilize a high-speed clock as a timebase fed to a counter gated by the pulse width to be measured. Such designs are limited in resolution to the time period of the timebase clock.